1. Field of the Invention
The present invention relates to a semiconductor device having a mark section and a dummy pattern around the mark section, and more particularly, relates to a dummy pattern for chemical-mechanical polishing (CMP) purpose formed on a dicing line or on an actual chip region in a semiconductor device.
2. Background Art
Recently, in association with miniaturization of the structure of a semiconductor device, a process employing a chemical-mechanical polishing (CMP) technique has been sought. For instance, CMP is inevitably employed in a case where a shallow trench isolation (STI) structure is to be brought into element isolation in a field oxidation process, or in the case of a planarization process for smoothing an interlayer film introduced for improving a margin for photolithography.
There will be described a method of manufacturing a conventional semiconductor device including an abrasion process using the conventional CMP technique; primarily, manufacturing processes relevant to a dicing line.
FIGS. 19 through 21 are schematic representations for describing a dicing line used in a process for manufacturing a conventional semiconductor device. FIG. 19 is a schematic enlarged plan view showing a dicing line formed on the surface of a semiconductor substrate. FIGS. 20 and 21 are schematic cross-sectional views taken along line XXxe2x80x94XX and XXIxe2x80x94XXI shown in FIG. 19.
In FIG. 19, a dicing line 100 runs vertically along the center of the drawing, and guardrings 200 are provided on opposite sides of the dicing line 100. A real chip region (an actual chip region) 300 exists outside the respective guardrings 200.
In FIGS. 19 through 21, reference numeral 1 designates a trench isolation region; 2 designates an active region; 3 designates a first contact hole; 4 designates a third wiring pattern; 5 designates a second contact hole; 6 designates a fourth wiring pattern; 7 designates a first wiring pattern; and 8 designates a mark forbidden region where marks are forbidden.
FIGS. 22 through 28 are descriptive views for describing steps of forming a shallow trench isolation (STI) structure in the process for manufacturing a conventional semiconductor device. These drawings show a case where residues arise in the STI structure forming step, in connection with the schematic cross-sectional view of the conventional dicing line 100 taken along line XXIxe2x80x94XXI shown in FIG. 21.
As shown in FIG. 22, an underlying oxide film 10, a polysilicon film 11, and a nitride film 12 are formed, in this sequence in an active region 2 of the semiconductor substrate.
As shown in FIG. 23, a photoresist film 13 is patterned on the nitride film 12.
As shown in FIGS. 24 and 25, the silicon nitride film 12, the polysilicon film 11, and the underlying oxide film 10 are patterned while the photoresist film 13 is taken as a mask. Further, the semiconductor substrate is etched so as to form a groove in the active region 2, thus forming a trench.
As shown in FIG. 26, for example, a silicon oxide film is formed as a trench isolation dielectric film on the semiconductor substrate in order to form a trench region 1 in the trench.
As shown in FIG. 27, the silicon oxide film is removed from the nitride film 12 by means of the CMP technique. In this case, etch residues, such as a residual oxide film 1a, is likely to remain on the nitride film 12.
As shown in FIG. 28, if such a semiconductor substrate is etched and patterned, the residual oxide film 1a acts as a mask, thereby forming an undesired pattern.
Here, the underlying oxide film 10 has a thickness of, for example, 100 angstroms; the polysilicon film 11 has a thickness of, for example, 500 angstroms; the nitride film 12 has a thickness of, for example, 1500 angstroms; and the photoresist film 13 has a thickness of, for example, 5000 angstroms.
FIGS. 29 through 31 are descriptive views for describing a CMP abrasion step employed in a process for manufacturing a conventional semiconductor device. These drawings show a process flow followed in the event that the corners of the pattern are abraded excessively (resultant recesses will hereinafter be referred to as xe2x80x9cdishingxe2x80x9d) when an interlayer insulating film formed on the first wiring pattern is abraded by means of the CMP technique.
As shown in FIG. 29, the trench regions 1 are formed so as to oppose the active region 2 of the semiconductor substrate interposed therebetween, and the first wiring pattern 7 is formed on the active region 2 as a mark.
As shown in FIG. 30, a first interlayer insulating film 14 is formed on the active region 2 and the first wiring pattern 7.
As shown in FIG. 31, the first interlayer insulating film 14 is abraded by means of the CMP technique. At this time, angular portions (corners) of the first wiring pattern 7 are likely to be exposed as a result of removal of the first interlayer insulating film 14, resulting in formation of so-called xe2x80x9cdishingxe2x80x9d.
FIG. 32 shows the photoresist film 13 formed on the semiconductor substrate shown in FIG. 31, where the photoresist film 13 does not have a uniform thickness but has an irregular thickness.
Of the foregoing manufacturing processes, the CMP abrasion process greatly depends on the density, size, and geometry of a pattern, hence the corners of the pattern in the vicinity of etch residues caused by abrasion suffers a problem of being excessively abraded (being prone to becoming xe2x80x9cdishingxe2x80x9d). Alternatively, a low-density region of the pattern is also prone to being excessively abraded.
Further, the entirety of the conventional dicing line 100 is usually formed on an active region, and patterns other than various marks or side monitors does not exist in the dicing line 100. Further, a silicon oxide film tends to remain on a silicon nitride (SiN) film in the CMP abrasion step during the process for forming the STI structure.
The present invention has been conceived to solve these problems, and the object of the present invention is to provide a semiconductor device having a dicing line or an actual chip structure, which mitigates the problems associated with the CMP abrasion step.
According to one aspect of the present invention, a semiconductor device comprises a plurality of real chip regions and at least a dicing line to separate the real chip regions respectively formed on the semiconductor substrate. A mark section is defined in the dicing line or in the real chip regions. A mark forbidden region is formed to surround the mark section with a predetermined width in the dicing line or in the real chip regions. A dummy wiring pattern is formed so as to fill the dicing line or a portion of the real chip region to integrally and continuously surround the mark section and the mark forbidden region.
According to another aspect of the present invention, in a semiconductor device, a first dummy wiring pattern is formed so as to fill the dicing line or a portion of the real chip region to integrally and continuously surround the mark section and the mark forbidden region. An interlayer insulating layer is formed on the first dummy wiring pattern. Further, a second dummy wiring pattern is formed on the interlayer insulating layer so as to fill the dicing line or a portion of the real chip region to integrally and continuously surround the mark section and the mark forbidden region.
Other and further objects, features and advantages of the invention will appear more fully from the following description.